Field of the Invention
This disclosure directs itself to a system-on-chip having a built-in self test and repair function for use with a memory formed by a plurality of stacked memory integrated circuit dies connected to the system-on-chip. In particular, the disclosure is directed to a system-on-chip having a memory controller that tests the memory connected to the system-on-chip and repairs faults detected by those tests. More in particular, the disclosure pertain s to a memory controller having a built-in self-test module system for testing the memory for defects and repair of the memory by substitution of redundant memory portions for those portions identified as being defective. Further, the disclosure relates to a built-in self-test system of a memory controller that includes a control processor and a first state machine sending data to the memory and reading data from the memory in sequential steps to test the memory for defective portions thereof responsive to commands from the control processor. Still further, the disclosure concerns a built-in self-test system that includes a first state machine sending data to the memory and reading data from the memory in sequential steps to test the memory for defective portions thereof, and a second state machine for executing sequential repair steps to replace the defective memory portions with redundant portions provided in the memory responsive to commands from the control processor. Additionally, the disclosure is directed to a method for configuring a system-on-chip for testing and repair of a 3D-IC memory connected thereto.
Prior Art
Traditionally, semiconductor memory chips have been subject to post-fabrication testing by the semiconductor manufacturer to detect defective memory elements that occur in chip fabrication with some regularity. As it is not economically feasible to reject all chips found to include any defective memory elements, on-chip repair techniques were developed to improve production yield. A commonly used on-chip repair technique uses the concept of replacing defective memory elements in a chip with spare memory elements that are also included in the chip. As memory arrays are made up of memory elements identified by rows and columns and may also be subdivided into multiple blocks. Redundant rows, columns and/or blocks are added to the memory integrated circuit die to accommodate the replacement of bad elements. Subsequent to substitution of redundant memory elements for those found to be defective, the semiconductor manufacturer would package the integrated circuit die and ship the memory to a customer.
The development and growth of system-on-chip architectures and the need for higher speed systems has led to unpackaged memory integrated circuit dies being mounted directly on system-on-chip substrates and the use of built-in self-test circuitry incorporated in the system-on-chip to identify assembly defects. With the need for increases in memory capacity and density unpackaged memory integrated circuit dies are now stacked on the system-on-chip and interconnected through vias formed in the integrated circuit substrates. This process creates new opportunities for introducing defects in the memory array and requires post assembly testing that duplicates many of the post-fabrication testing done by the semiconductor manufacturer. It would therefore be more efficient to expand the capability of the built-in self-test function to perform the testing that heretofore was performed by the semiconductor manufacturer and add the repair capability as well. However, as each semiconductor manufacturer uses their own selection of tests to detect faults and their own procedures to substitute redundant memory elements, and different types of memory circuits require different tests to detect faults as well, any built-in self-test and repair capability incorporated into a system-on chip must be able to accommodate various memory types and memory integrated circuit dies and memory integrated circuit dies from multiple sources.